A number of integrated circuits are typically fabricated at the same time on a common slice of silicon or wafer. This wafer is usually substantially circular with a diameter of around 3 to 6 inches (7.5 to 15 cm). Once the fabrication process is complete, the wafer is then sliced-up into the individual integrated circuit (IC) chips or dice (singular: die) which are later packaged into modules or incorporated into larger systems.
This process of dividing a wafer into its individual dice involves scribing the wafer with grooves, then breaking the wafer along those grooves like pieces of a chocolate bar. Alternatively, the dice are cut from the wafer using a saw or laser. Sometimes, the entire dividing process is referred to as "scribing". When the dice are still connected as an integral wafer or separated but closely packed together as if they still were a wafer, the IC's are said to be in the wafer scale or level of development having wafer scale equivalent density.
Typically, after scribing, IC dice are packaged individually into separate modules to be used in creating larger systems. However, to further reduce the size of the eventual system, more than one IC may be packaged in a single module called a Multi-Chip Module (MCM). As with any wafer scale system, the dice being in close proximity to each other allow for greater speed and less power consumption. However, completed MCM's are not easily repairable and require substantial design modification when different IC's are to be used.
As IC's evolved, the die size and device package pinouts were not standardized, but driven by a manufacturer's customer base and technology. Eventually, standardized IC packages and pinouts were developed. to allow interchangability among vendors. Over time, the bare dice became more robust (moisture resistance, tensil strength, etc.), allowing MCM technology to develop. But, as one vendor's dice are designed into an MCM, another vendor's dice will not fit due to different die pinouts. It is possible, however, to achieve some degree of standardization by re-routing a die's connections to a secondary set of pads elsewhere on the die. The size of these secondary pads can also vary depending on the packaging method used.
The next logical step in miniaturization for the semiconductor electronics industry involves wafer scale integration. Basically, this means closely packing the dice used in a system so that they have the same density they enjoyed when they were connected as a wafer. This reduces the size of the overall circuitry, increases speed, and lowers cost. Although technically one could produce most all of the electronics necessary in a system on a single wafer, this approach presents many problems. Defective regions on IC's which render some devices useless are quite common. This requires redundant circuitry designed into the chip, which in turn takes up more space. More desirable would be a way of replacing those defective portions of the wafer while still maintaining circuit density.
Due to their junction temperatures, IC's are the most statistically significant determinate of reliability in most electronic systems, and a major factor in overall product reliability. Maintaining a high thermal conduction path for IC's is important. Heat build up is prevented where the junction temperature is the same for each die as occurs with wafer scale densities, allowing higher reliability along with a more integrated package. Additionally, some IC's benefit from or are required to operate in a cooled environment.
Most IC's that are going to fail before a reasonable lifetime do so at an early stage. Therefore, these units may be screened out by running all the IC's for a time and then testing prior to shipment. This weeding out process can be hastened by elevating the temperature and applying voltages either statically or dynamically to the IC's. This process is called burn-in. In the past, this required the placing the packaged IC module into a special oven or autoclave capable of applying the proper burn-in voltages or signals.
Wafer scale testing of IC's involves using a test probe. In a time-consuming procedure, the probe must be precisely aligned with each die to be tested, one at a time.
Currently, in the industry there is no known device which accomplishes easily repairable wafer scale integration.